Virtual Instruction Set Computing for Heterogeneous Systems

Developing software applications for emerging and future heterogeneous systems with diverse combinations of hardware is significantly harder than for homogeneous multicore systems. In this paper, we identify three root causes that underlie the programming challenges: (1) diverse parallelism models; (2) diverse memory architectures; and (3) diverse hardware instruction set semantics. We believe that these issues must be addressed using a language-neutral, virtual instruction set layer that abstracts away most of the low-level details of hardware, an approach we call Virtual Instruction Set Computing. Most importantly, the virtual instruction set must abstract away and unify the diverse forms of parallelism and memory architectures using only one or two models of parallelism. We discuss how this approach can solve the root causes of the programmability challenges, illustrate the design with an example, and discuss the research challenges that arise in realizing this vision.